The silicon bipolar transistor has been the device of choice for high power applications in motor drive circuits, appliance controls, robotics and lighting ballasts. This is because bipolar transistors can be designed to handle relatively large current densities in the range of 40-50 A/cm.sup.2 and support relatively high blocking voltages in the range of 500-1000 V.
Despite the attractive power ratings achieved by bipolar transistors, there exist several fundamental drawbacks to their suitability for all high power applications. First of all, bipolar transistors are current controlled devices which require relatively large base currents, typically one fifth to one tenth of the collector current, to maintain the transistor in an operating mode. Proportionally larger base currents can be expected for applications which also require high speed turn-off. Because of the large base current demands, the base drive circuitry for controlling turn-on and turn-off is relatively complex and expensive. Bipolar transistors are also vulnerable to premature breakdown if a high current and high voltage are simultaneously applied to the device, as commonly required in inductive power circuit applications. Furthermore, it is relatively difficult to operate bipolar transistors in parallel because current diversion to a single transistor typically occurs at high temperatures, making emitter ballasting schemes necessary.
The silicon power MOSFET was developed to address this base drive problem. In a power MOSFET, the gate electrode provides turn-on and turn-off control upon the application of an appropriate gate bias. For example, turn-on in an N-type enhancement MOSFET occurs when a conductive N-type inversion layer is formed in the P-type channel region in response to the application of a positive gate bias. The inversion layer electrically connects the N-type source and drain regions and allows for majority carrier conduction therebetween.
The power MOSFET's gate electrode is separated from the channel region by an intervening insulating layer, typically silicon dioxide. Because the gate is insulated from the channel region, little if any gate current is required to maintain the MOSFET in a conductive state or to switch the MOSFET from an on-state to an off-state or vice-versa. The gate current is kept small during switching because the gate forms a capacitor with the MOSFET's channel region. Thus, only charging and discharging current ("displacement current") is required during switching. Because of the high input impedance associated with the insulated-gate electrode, minimal current demands are placed on the gate and the gate drive circuitry can be easily implemented.
Moreover, because current conduction in the MOSFET occurs through majority carrier transport only, the delay associated with the recombination of excess minority carriers is not present. Accordingly, the switching speed of power MOSFETs can be made orders of magnitude faster than that of bipolar transistors. Unlike bipolar transistors, power MOSFETs can be designed to withstand high current densities and the application of high voltages for relatively long durations, without encountering the destructive failure mechanism known as "second breakdown". Power MOSFETs can also easily be paralleled, because the forward voltage drop of power MOSFETs increases with increasing temperature, thereby promoting an even current distribution in parallel connected devices.
In view of these desirable characteristics, many variations of power MOSFETs have been designed. Two popular types are the double-diffused MOS (DMOS) device and the ultra-low on-resistance MOS device (UMOS). The DMOS structure and its operation and fabrication are described in the textbook by inventor Baliga entitled Modern Power Devices, the disclosure of which is hereby incorporated herein by reference. Chapter 6 of this textbook describes power MOSFETs at pages 263-343. FIG. 1 herein is a reproduction of FIG. 6.1(a) from the above cited textbook, and illustrates a cross-sectional view of a basic DMOS structure. The DMOS structure is fabricated using planar diffusion technology.
The UMOS device, also referred to as a "Trench DMOS" device, is described in publications entitled: An Ultra-Low On-Resistance Power MOSFET Fabricated by Using a Fully Self-Aligned Process, by Ueda et al., IEEE Transactions on Electron Devices, Vol. ED34, No. 4, April (1987), pp. 926-930; Numerical and Experimental Comparison of 60 V Vertical Double-Diffused MOSFETS and MOSFETS with a Trench-Gate Structure by Chang, Solid State Electronics, Vol. 32, No. 3, pp. 247-251 (1989); Trench DMOS Transistor Technology for High-Current (100A Range) Switching by Bulucea et al., Solid State Electronics, Vol. 34, No. 5, pp. 493-507 (1991); and Extended Trench-Gate Power UMOSFET Structure with Ultralow Specific On-Resistance, by Syau et al., Electronics Letters, Vol. 28, No. 9, pp. 865-867 (1992). FIG. 2 herein is a reproduction of a portion of FIG. 1 of the above identified Ueda et al. publication illustrating an embodiment of the UMOS structure.
A third example of a silicon power MOSFET is shown in FIG. 3. FIG. 3 is a reproduction of FIG. 4 from U.S. Pat. No. 4,903,189 to Ngo et al. and inventor Baliga, the disclosure of which is hereby incorporated herein by reference. This MOSFET 170, which includes trenches 178 at a face thereof and contains no P-N junctions, is commonly referred to as an accumulation-mode FET ("ACCU-FET") because turn-on is achieved by forming a conductive accumulation layer between the FET's source 186 and drain 182 regions. FIG. 3 shows a plurality of parallel connected ACCU-FET cells, each defined by mesas 179 and opposing trenches 178.
A fourth example of a vertical power MOSFET is shown in FIG. 4A. FIG. 4A is a reproduction of FIG. 3 from U.S. Pat. No. 5,168,331 to H. Yilmaz. In particular, this MOSFET includes a "free floating" shield region 30 (P or N-) which serves as a buffer to reduce the strength of the electric field at point 18, which is adjacent to a corner in the profile of the gate 12.
The above-described beneficial characteristics of power MOSFETs are typically offset, however, by the relatively high on-resistance of the MOSFET's channel region, which arises from the absence of minority carrier injection. As a result, a MOSFET's operating forward current density is typically limited to relatively low values, typically in the range of 10 A/cm.sup.2, for a 600 V device, as compared to 40-50 A/cm.sup.2 for the bipolar transistor.
On the basis of these features of power bipolar transistors and MOSFET devices, hybrid devices embodying a combination of bipolar current conduction with MOS-controlled current flow were developed and found to provide significant advantages over single technologies such as bipolar or MOSFET alone. One example of a hybrid device is the Insulated Gate Bipolar Transistor (IGBT), disclosed in section 7.2 of the aforementioned Baliga textbook.
The IGBT combines the high impedance gate of the power MOSFET with the small on-state conduction losses of the power bipolar transistor. An added feature of the IGBT is its ability to block both forward and reverse bias voltages. Because of these features, the IGBT has been used extensively in inductive switching circuits, such as those required for motor control applications. These applications require devices having wide forward-biased safe-operating-area (FBSOA) and wide reverse-biased safe-operating-area (RBSOA).
One embodiment of an IGBT is disclosed in an article by inventor B. J. Baliga and M. S. Adler, R. P. Love, P. V. Gray and N. Zommer, entitled The Insulated Gate Transistor: A New Three terminal MOS Controlled Bipolar Power Device, IEEE Trans. Electron Devices, ED-31, pp. 821-828 (1984), the disclosure of which is hereby incorporated herein by reference. Based on experimental results, on-state losses were shown to be greatly reduced when compared to power MOSFETs. This was caused by the conductivity modulation of the IGBT's drift region during the on-state. Moreover, very high conduction current densities in the range of 200-300 A/cm.sup.2 were also achieved. Accordingly, an IGBT can be expected to have a conduction current density approximately 20 times that of a power MOSFET and five (5) times that of an equivalent bipolar transistor. Typical turn-off times for the IGBT can be in the range of 10-50 .mu.s.
The basic structure of the IGBT is shown in cross-section in FIG. 5A, which is a reproduction of FIG. 1 from the aforementioned Baliga et al. article. In the IGBT, forward conduction can occur by positively biasing the anode (or electron "collector") with respect to the cathode (or electron "emitter") and applying a positive gate bias of sufficient magnitude to invert the surface of the P-base region under the gate. By creating an inversion layer in the P-base region, electrons are allowed to flow from the N+ emitter region to the N-base region. In this forward conducting state, the junction J2 is forward biased and the P+ anode region injects holes into the N-Base region. As the anode bias is increased, the injected hole concentration increases until it exceeds the background doping level of the N-base. In this regime of operation, the device operates like a forward-biased P-i-N diode with heavy conductivity modulation of the N-base region. In the reverse bias region, the anode is biased negative with respect to the cathode and the lower junction (J3) is reversed biased, thereby preventing conduction from the cathode to anode even though the upper junction (J2) is forward biased. This provides the device with its reverse blocking capability.
Another IGBT which includes a "free floating" shield region for improving the reverse blocking capability is shown in FIG. 4B, which is a reproduction of FIG. 10 from the aforementioned '331 patent to Yilmaz. In particular, this IGBT includes a "free floating" shield region 85 (P or N-) which serves as a buffer to reduce the strength of the electric field at point 87, which is adjacent to a corner in the profile of the gate 82.
The IGBT can typically operate at high current densities even when designed for operation at high blocking voltages. As long as the gate bias is sufficiently large to produce enough inversion layer charge for providing electrons into the N-base region, the IGBT forward conduction characteristics will look like those of a P-i-N diode. However, if the inversion layer conductivity is low, a significant voltage drop will begin to appear across this region like that observed in conventional MOSFETs. At this point, the forward current will saturate and the device will operate in its active or current saturation region, as shown in FIG. 5B, which is a reproduction of FIG. 2 from the aforementioned Baliga et al. article. As will be understood by those skilled in the art, high voltage current saturation is ultimately limited by avalanche induced breakdown. Finally, because the elimination of the inversion layer cuts off the supply of electrons into the N-base region and because there is no self-sustaining source of electrons to the N-base region, the IGBT will typically turn off even if the anode remains positively biased.
One significant drawback to the operation of IGBTs is the presence of a parasitic P-N-P-N structure between the anode and cathode which can cause a loss in the gate controlled turn-off capability by becoming regenerative at high current densities. The current level at which parasitic thyristor latch-up occurs provides a limit to FBSOA at low anode voltages, while at high anode voltages, FBSOA is limited by dynamic avalanche breakdown.
As will be understood by one skilled in the art, latch-up can be prevented so long as the sum of the current gains of the regeneratively coupled P-N-P and N-P-N transistors (.alpha..sub.pnp, .alpha..sub.npn) is less than unity. To inhibit the likelihood of latch-up operation, the current gain of the N-P-N transistor (.alpha.npn) can be made relatively small by reducing the P-base sheet resistance and/or the width of the N.sup.+ source region. This suppresses electron injection from the N.sup.+ source region to the P-base because the uppermost P-N junction between the P-base and N.sup.+ source is effectively short circuited, thereby eliminating the regenerative P-N-P-N path from between the anode and cathode.
However, as described in an article by J. P Russell, A. M. Goodman, L. A. Goodman and J. M. Neilson, entitled The COMFET-A New High Conductance MOS-Gated Device, IEEE Electron Device Letters, Vol. EDL-4, No. 3, March (1983), pp. 63-65, even devices having a relatively low P-base sheet resistance can be susceptible to regenerative latch-up if sufficiently large forward current densities cause significant emitter injection into the base of the N-P-N transistor (P-base) and cause .alpha..sub.npn to increase. To reduce the likelihood of parasitic latch-up, the COMFET structure was modified to include a heavily doped P.sup.+ region in the middle of the P-base region, electrically connected to the cathode contact.
Other attempts have also be made to reduce the IGBT's susceptibility to latch-up. For example, in an article by A. M. Goodman, J. P. Russell, L. A. Goodman, C. J. Nuese and J. M. Neilson, entitled Improved COMFETs with Fast Switching Speed and High-Current Capability, IEEE International Electron Devices Meeting Digest, Abstract 4.3, (1983), pp. 79-82, a highly doped (N.sup.+) epitaxial layer was formed on top of the P.sup.+ anode region at junction J3 in order to lower the gain of the lower P-N-P transistor (.alpha..sub.pnp) and thereby reduce the likelihood of parasitic latch-up at high current densities.
A hole-bypass technique involving the elimination of one of the two uppermost N-type emitter regions from the uppermost P-base region is also described in an article by A. Nakagawa, H. Ohashi, M. Kurata, H. Yamaguchi and K. Watanabe, entitled Non-Latch-Up 1200v 75A Bipolar-Mode MOSFET with Large ASO IEEE International Electron Devices Meeting Digest, Abstract 16.8, (1984), pp. 860-861. By eliminating the emitter region on one side of the P-base, the hole current collected by the base on that side is provided to the cathode contact without having to travel around an N.sup.+ emitter region. This bypass technique reduces the likelihood that the uppermost P-N junction between the P-base and N.sup.+ emitter will become forward biased at high current densities.
Another attempt to reduce the IGBT's susceptibility to latch-up is disclosed in U.S. Pat. No. 5,396,087 to Baliga entitled Insulated Gate Bipolar Transistor With Reduced Susceptibility to Parasitic Latch-Up, by inventor Baliga, the disclosure of which is hereby incorporated herein by reference. In this IGBT, injection suppressing means is provided between the N+ emitter and P-base region to prevent minority carrier injection from the N+ emitter to the P-base when the anode is biased positive relative to the cathode. Injection suppressing means preferably includes an electrical insulator such as SiO.sub.2.
Notwithstanding these attempts to develop improved IGBTs for high power applications, there still exists a need to develop semiconductor switching devices which have low on-state resistance and high reverse blocking voltage capability. There also exists a need for switching devices which have wide forward safe-operating-area (SOA) and excellent current saturation characteristics.